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Design And Fpga Implementation Of Neural Network
Author name:
مثنى حاجم حمد العامري
General topic:
Control and Systems Engineering
Specific topic:
Control and systems engineering
Degree:
Doctorate
University:
Mustansiriyah University - College Of Engineering - Department Of Electrical Engineering
Language:
English
University location:
Baghdad
First pages:
34T537 - p.pdf
Abstract:
The use Artificial Neural Networks (ANN) can be a form of Artificial Intelligence (AI). The feedforward neural network has a wide application area such as pattern recognition, image compression, and classification problem. Two models of a feedforward neural network are proposed and implemented using the schematic editor of the Xilinx foundation series 2.1i. Model - 1 consists of two layers and specializes in solving linear problems. Depending on the type of application, the input layer can receive 2 to 126 input values ordered in 256x16bits RAMs. The connection weights are distributed over four 256x16bits RAMs where, the four RAMs exchange their active role in swapping operation. Model - 2 is a modified copy from Model - 1 and consists of three layers and it is responsible for classifying non - linear problems.The mathematical model of the data set (weights and inputs) is presented in a matrix multiplication format. Principle Component Analysis (PCA) is a modern method used to reduce patterns set dimensionality and hence speeds up the training phase iterations. Speeds up the training phase will eventually minimize the over all system execution time. Each model is designed and implemented in five stages without using the finite state machine. It controls the processes of the forward propagation phase, error calculation, and training algorithm. These processes are managed by many control circuits like, J - K synchronized circuit, sign - detector/sum - sub control circuit, and timers that takes the role of finite state machine. These five stages make the design easily to implemented and modified. Modification in the system parameters (No. of inputs, No. of outputs, or No. of layers) can be performed in the appropriate stage without reservation.The flexibility, low costly, and real - time operation are the main features of the proposed design. Model - 1 execution time is 2.935µs and model - 2 execution time is 2.96µs, while the costs of two models are 1927 and 2017 CLBs respectively.These features compare extremely well with other existing designs with good advantages.
