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تصميم وتنفيذ معالج باستخدام TM - CFAR مصفوفة البوابات المبرمجة FPGA == Design And Implementation Of TM - CFAR Processor Using Field Programmable Gate Array
Author name:
علي هادي عبد الواحد
Supervisor name:
وليد خالد عبد علي
General topic:
Electrical, Electronic and Communications Engineering
Specific topic:
Electronics and Communications Engineering
Degree:
Master
University:
Mustansiriyah University - College Of Engineering - Department Of Electrical Engineering
Language:
English
University location:
Baghdad
First pages:
34T536 - p.pdf
Abstract:
This Thesis proposes on a project whose aim is to implement architectures for CFAR processor employed in radars. These proposed architectures are implemented by using Field Programmable Gate Array (FPGA) technique, with observance of feature desired as flexibility and speed without performance loss. This design written in VHDL Hardware Description Language that can be used to accelerate the implementation. In this thesis, the proposed by design is implemented using MATLAB Simulink on the Trimmed - mean Constant False Alarm Rate Processor(TM CFAR) to obtain system parameters and to test the flow of signal through the system, and then used FPGA devices. FPGA architecture of TM - CFAR processor is implemented to overcome the large processing time required in case of multi - target environment. The use of this technology is suitable because it offers high flexibility in modifying and even developing the required design with a reduction in the required number of hardware and cost. In addition to the main features of the processing chain architectures such as degree of parallelism, small size, accuracy and high computational speed, there is a requirement for generality and adaptively i.e. the ability to handle many different models of operation in different environments. The FPGA implementation of the design is achieved using Xilinx Virtex - II platform as a suitable selected programmable device. The development of the system software for this work has been done using Active HDL 3.5, and ISE Navigator 6.3i programs.
