تحقيق دائرة المعدل الثابت للانذار الكاذب باستعمال منظومة البوابات المنطقية المبرمجة موقعيا == Modified GO - CFAR Implementaion Using FPGA
Author name:
مصطفى صبحي كمال
Supervisor name:
رفعت طالب حسين | حكمت نجم عبد الله
General topic:
Electrical, Electronic and Communications Engineering
Specific topic:
Electrical Engineering
Degree:
Master
University:
Mustansiriyah University - College Of Engineering - Department Of Electrical Engineering
Language:
English
University location:
Baghdad
First pages:
34T541 - p.pdf
Abstract:
هذه الاطروحة تتعلق بتحليل ومعالجة تاثير الضوضاء المحيطية (Clutter) لمنظومة الرادار النبضي، يتطلب رادار الكشف الالي للهدف استعمال عتبة الية (Adaptive threshold) لتحقيق معدل ثابت للانذار الكاذب وذلك لغرض السيطرة على الانذار الكاذب الذي تسببه تغيرات في الضوض | This thesis deals with the analysis and processing of clutter for pulsed radar system. Automatic target detection radar requires adaptive thresholding achieved by Constant False Alarm Rate (CFAR) circuit in order to control the false alarm caused by variations in clutter background.This work focus on worst radar environment that happens when abrupt variation in clutter background merged with multi - interfering target, to detect target in such environments it need robust CFAR algorithm that excise the target spikes and clutter edges from CFAR window in order to give best possible estimation to the noise background. two important algorithms studied which are CA - CFAR and OS - CFAR algorithms in additional to the modified CA - CFAR algorithm. All these algorithms were simulated with mat lab v6.1 and applied them to three different clutter models that represent different environment cases the CA - CFAR family failed to handle model two and three also OS - CFAR family except OSGO - CFAR that handle all models successfully. For modified CA - CFAR family only modified GO - CFAR handle all models successfully and comparing with OSGO - CFAR the modified GO - CFAR need less hardware and processing time because it did not need sorting process that is essential for OSGO - CFAR. Therefore, the modified GO - CFAR is chosen to implement by using FPGA and another important feature in modified GO - CFAR algorithm that is parallel processing since the spike selection process is done at the same time with summing of samples process that make this algorithm much less in processing time from any other algorithm that work in the same environment. The FPGA chip that used to implement modified GO - CFAR algorithm need only three signals from the radar receiver to mach with the receiver circuit correctly which are time base clock signal period reset trigger signal and the pulse duration time. Therefore, the FPGA chip can work effectively with almost any radar receiver system
